TSMC revealed new details about its next state-of-the-art manufacturing process, 3nm, which for now will be specific to my main client: Apple.
According to the latest information revealed by the company, Its 3nm allows it to increase speed by 10 to 15 percent Same energy consumption as your manufacturing process 5nm (v1.0).
If performance is not one of the priorities, but autonomy 3nm . with the same speed as silicon 25 to 30 percent less energy consumptionAll this by increasing the logic density by 70%, the SDRAM density by 20%, and the analog density by 10%.
On the other hand, the representative of a company, dr yuh jier mi, said that the 3nm manufacturing process Has doubled the number of “tape-outs” in its first year compared to 5nm. The term “taped-out” refers to chip designers who finalize their designs before sending them to the factory, which is responsible for refining them or going into production.
While he hasn’t explicitly linked TSMC’s work on nanoscale transistors to its 2nm process, Dr. Mi shared key details of the circuits that could represent his company’s biggest manufacturing leap in years. He highlighted that nanoscale transistors have managed to implement Strict control of threshold voltage (VT). In semiconductor design, Vt refers to at the minimum voltage required For a circuit to function, and even the smallest variations can introduce design limitations and performance drops.
According to the manager, the nanoscale transistor has achieved “demonstrate that nanoscale transistors have 15% smaller Vt variations, as shown in blue, than FinFET transistors, as shown in red“.
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